1. Field of the Invention
The present invention generally relates to integrated circuits and, in particular, to systems and methods for facilitating, within an integrated circuit, receiver trip level testing of pads of the integrated circuit.
2. Description of the Related Art
Heretofore, integrated circuit (IC) devices have been tested and verified using a variety of test methods. For example, IC devices have been tested and verified to be defect-free using functional test vectors, such as those applied to the IC by the use of automated test equipment (ATE), which stimulate and verify the IC device functionality at the pin level of the device. A practical limitation to the utilization of ATE for testing IC's, however, is that the number of IC pins (or pads) that can be tested by a particular ATE has, heretofore, been limited by the physical configuration of the ATE. For instance, the number of pads of the IC to be tested may exceed the number of test channels provided by an ATE, or the number of pads may exceed the capacity of the ATE support hardware, such as by exceeding the maximum number of probes on a probe card, among others. As utilized herein, the term “pad” is used to refer collectively to both a physical site, which serves as an electrical contact for an IC, as well as circuitry associated with the physical site for enabling electrical communication between components of the IC and components external to the IC.
Additionally, performance limitations of a particular ATE may impose certain other testing restrictions. For example, the frequency of IC inputs and outputs may exceed the maximum frequency of the ATE, thereby limiting the test frequency of the IC to be tested to the maximum frequency of the ATE. Although configuring an ATE with additional test channels and/or a higher operating frequency may be accomplished, providing an ATE with an appropriately high pin count and/or an appropriately high operating frequency in order to eliminate the aforementioned deficiencies is, oftentimes, cost prohibitive.
In light of the foregoing and other deficiencies, it is known in the prior art to test IC devices utilizing a variety of “stop-gap” testing procedures, including: (1) connecting an ATE to less than all of the pins of an IC device; (2) connecting multiple pins of an IC device to a single ATE test channel; (3) testing the IC device in multiple passes of the ATE, with each pass testing a subset of the pins of the entire IC device; (4) testing the device at less than maximum frequency, and; (5) limiting, through design implementation, the pin count and/or frequency of the IC device to accommodate existing ATE, among others. As should be readily apparent, many of these “stop-gap” testing procedures may result in a loss of test coverage and, thereby, may lead to an increase in numbers of defective IC devices being shipped. Moreover, the practice of limiting, through design implementation, the pin count and/or frequency of the IC device to accommodate existing ATE is, oftentimes, an unacceptable constraint on IC design.
Therefore, there is a need for improved systems and methods which address these and other shortcomings of the prior art.